International Patent Application No. 99/19806 describes a bus system in which signals are transmitted at a constant frequency between individual units connected to the bus. If such a signal is sent to the bus by a first unit connected to the bus, the signal is delayed due to the signal transit time, especially in the case of very long bus systems and, in particular, because of the switching times in other units connected to the bus. If the signal is then looped back to the first unit connected to the bus, the signal is usually phase shifted with respect to the emitted signal and therefore with respect to the operating clock of the first unit, while the frequency of the signal itself is still the same. When the signal looped back to the first unit is sampled, the phase shift may cause errors, in particular in the case when the looped-back signal changes during just a period of time when a readout device in the first unit switches according to the operating clock of the first unit. In such a unit, an input signal is sent to two flip-flops, one flip-flop receiving the signal applied to a data input with a rising edge of the receiving device's operating clock and the second flip-flop with a falling edge of the receiving device's operating clock. The phase of the operating clock is compared to the phase of the input signal using a phase measuring circuit, and either the output signal of the fist flip-flop or the output signal of the second flip-flow is selected via a multiplexer for further processing as a function of the measured phase. The flip-flops are controlled using the operating clock of the receiving device; therefore, the new signals are synchronized with the operating clock of the receiving device.
A square signal 3 corresponding to the operating clock is shown in FIG. 2 as a function of time. Time periods 6 for the input into the first flip-flop during which the input signal is allowed or is not allowed to change are shown for square signal 3. Furthermore, similar time periods 7 are shown for the second flip-flop, in which the input signal is allowed or is not allowed to change. For the flip-flop which switches to a falling clock edge 2, the input signal is not allowed to change in a time period 4, since during the switching period of the flip-flop the status is indefinite and therefore detection of the data signal during this period may cause errors. During the remaining time periods 5, however, the input signal may change. For time periods 7 for the flip-flop switching to a rising clock edge 1, a distinction is also made between allowed time periods 5′ and unallowed time periods 4′ in the vicinity of the rising clock edge. Unallowed time periods 4, 4′ are disjoined in time, since the two clock edges are shifted with respect to one another by half a period, and the switching period of the flip-flops is less than half a period. The input signal is applied at a constant frequency, so that a change in the input signal occurs in a switching period always at the same phase angle, although at an unknown point in time. Therefore, this point in time is located either in an allowed time period 5 or in an allowed time period 5′, so that at least one correct signal is available. According to International Patent Application No. 99/19806, an output signal of one of the two flip-flops is selected by comparing the phase of the clock pulse of the input signal with that of the operating clock of the receiving device; at least one flip-flop must then output correct data assuming correct transmission. A complex circuit, requiring an integrator, i.e., an analog component, is required for determining the phase difference. In addition, a clock pulse of the input signal, which must also be transmitted, must be available.